1. Field of the Invention
The present invention relates to a test carrier for a semiconductor integrated circuit and a method of testing the semiconductor integrated circuit. More particularly, the present invention relates to a test carrier for holding a semiconductor integrated circuit subject to an accelerated test etc. and a method of testing the semiconductor integrated circuit by using the test carrier.
2. Description of the Prior Art
Recently, a high integration of the semiconductor integrated circuit (LSI) has been required and demand for downsizing of electronic devices has increased. In order to satisfy these requirements, not only the high integration of elements in the LSI is required but also a high density packaging technology of the semiconductor chip is required. Such high density packaging technology becomes dominant in the fields of bare chip packaging, a MCM (multi-chip module) and the like. And, under such situation, electrodes on a bare chip in the LSI and terminals of CSP (Chip Size Package) in the LSI are also formed with high density.
In the above circumstances, various attempts have been made to test the LSI as a bare chip.
Before the LSI is supplied to the user as a product in a bare chip state, both a thermally accelerated test (referred to as a Burn In (B.I) test hereinafter) and a Final Test (FT) are conducted in the bare chip state to detect initial defects of the LSI. In the B.I test, while heating the semiconductor integrated circuit, the various electric properties thereof are examined.
If a product like the MCM, in which a plurality of semiconductor chips are formed into one package, includes only one defect chip in the package, an entire product becomes defective. Therefore, the bare chip test is inevitably required for each individual bare chip. Thus, in the product in which a plurality of semiconductor chips are mounted in one package, each semiconductor chip must be subject to the B.I test in the bare chip state. Such test may be required with a greater degree of frequency in the future. However, regarding the B.I test conducted in the bare chip state, the testing technology at present has yet to be established.
In general, when the semiconductor integrated circuit formed on the semiconductor wafer is tested, a so-called PP (Production Probe) test has been frequently utilized wherein test probes electrically connected to the testing apparatus are contacted to minute electrodes formed on the surface of the semiconductor wafer.
A first test method may be considered to comprise the application of the PP test together with the use of the B.I test used for the bare chips of the semiconductor integrated circuit.
According to the first test method, as shown in FIG. 1, probes 1 connected to the electric characteristic detecting apparatus (not shown) are contacted to minute electrodes 2A formed on the surface of the semiconductor chip 2. In this situation, the probes 1 and the semiconductor chip 2 are then placed in the heating furnace. The B.I test is then carried out while the semiconductor integrated circuit on the semiconductor chip 2 is operated in the high temperature surrounding.
In addition, a second test method may be considered to comprise the application of the B.I test while directly contacting terminals of the IC socket to the electrodes of the bare chip. The terminals of the IC socket are used to test the semiconductor integrated circuit chip packaged by resin etc. Such IC socket is exemplified in FIG. 7.
Furthermore, as shown in FIG. 2A, a third test method may be considered to comprise the application of the B.I test of the semiconductor chip 2 under such conditions that electrodes 2A of the semiconductor chip 2 contact test electrodes 3B formed on the lower surface of the insulating polyimide test sheet 3 and that connecting wiring patterns 3A, which are formed on the upper surface of the test sheet 3 and connected to the test electrodes 3B, connect to the electric characteristic detecting apparatus.
However, in the above first, second and third test methods, the following problems occur:
In the first test method, as shown in FIG. 1, in order to contact the probes 1 to the minute electrodes 2A on the semiconductor chip 2, location displacements between many of probes 1 aligned in high density and the electrodes 2A of the semiconductor chip 2 must be first corrected by an image recognition technique before the probes 1 and the electrodes 2A are connected to each other. The probe 1 is in general very expensive. Moreover, it is not practical to provide an individual semiconductor chip with an alignment device. If this was done, cost would be enormously raised and thereof makes the semiconductor chip very expensive.
According to the second test method, in contrast to the electrodes of the semiconductor chip, top portions of the contact pins of the IC socket vary largely in size and location so that an increased alignment error results in between the IC socket and the semiconductor chip.
Further, it is difficult to increase the integration density of the contact pins of the IC socket correspondingly to a miniaturization of the electrodes of the semiconductor chip.
Moreover, according to the third test method, after the electrodes 3B on the test sheet 3 and the contact electrodes 2A of the semiconductor chip 2 are aligned, a location discrepancy between the electrodes 2A and the electrodes 3A is caused due to the vibration generated during the B.I test and the shock generated while carrying the test sheet 3, so that the third test cannot be effected satisfactorily. In addition, since the electrodes 3B of the test sheet 3 is formed minutely and the test sheet 3 is formed by the flexible film such as the polyimide film, stable contacts cannot be obtained between the contact electrodes 2A and the electrodes 3B of the contact sheet 3 unless the entire test sheet 3 is pressed uniformly against the semiconductor chip 2. It can be considered to bond both the electrodes 2A, 3A by solder. But, according to this method, it is hard to remove the semiconductor chip 2 from the test sheet 3 after the test is completed. Therefore, the semiconductor chip 2 so tested cannot be forwarded promptly as the product.
In addition, as the common drawback to the above first to third test methods, when, like the ordinarily packaged IC, the bare chip is tested by the B.I test in the air, defects such as a burning are caused because dusts are attached to the bare chip, and so on. When the chips are heated for a long time in the air, the electrodes of the semiconductor chip are oxidized and thus degraded. Thus packaging and connection characteristics of the semiconductor chip are lowered.
As described above, it is in fact extremely hard to conduct the B.I test in the bare chip state by means of the existing technologies.
Adjustment between electrodes on the bare chip and contact terminals on the testing substrate, and adjustment between terminals of CSP and the contact terminals on the testing substrate are indispensable. To align the bare chip and CSP, there has been the case where a testing substrate having adjustment walls or grooves thereon is used, for example. In general, such adjustment by the walls or the grooves is called as "mech-adjustment".
However, because the bare chips are separated by dicing of the semiconductor wafer, variations are caused in their outer size and their locations with respect to outer shapes of electrodes formed on the bare chip. As a result, the electrodes on the bare chip and the contact terminals on the testing substrate cannot be aligned with good precision. In addition, since a clearance to connect the testing substrate and the bare chip resides, displacement in location is easy to be caused in the clearance.
Hence, a method has been developed wherein adjustment between the electrodes on the bare chip and the contact terminals on the testing substrate is effected by image recognition technique. In this method, respective locations of the electrodes on the bare chip and the contact terminals on the testing substrate are recognized by an image processing apparatus, then locations of the electrodes and the contact terminals are compared with each other, and then displacement between them can be eliminated by moving the bare chip if displacement is recognized between the electrodes and the contact terminals.
In order to align the testing substrate with the bare chip and fix them, a holder 201 shown in FIGS. 3A and 3B has been used.
The holder 201 comprises a pushing plate 203 in which an air through-hole 202 is provided, and a latch portion 204. While a semiconductor device 220 as the bare chip is being held by pull force from a handling head 210 via the air through-hole 202 in the pushing plate 203, the semiconductor device 220 is aligned by means of the image recognizing apparatus, then the handling head 210 is descended to contact the electrodes 221 on the semiconductor device 220 and the contact terminals 223 on the testing substrate 222. In this case, the latch portions 204 are provided on both sides of the pushing plate 203, and the latch portions 204 are formed to engage with flanges 224 on the testing substrate 222.
Accordingly, the semiconductor device 220 is pushed and fixed by the pushing plate 203 against the testing substrate 222.
The holder 201 may also be used, as shown in FIG. 4, even in case the CSP type semiconductor device 230 is fixed to a testing substrate 32 to contact terminals 231 on a semiconductor 230 with contact terminals 233 on a testing substrate 232. In this event, latch portions 204 of the holder 201 are engaged with a bottom of the testing substrate 232 via latch holes 234.
However, in such holder 201, when the latch portions 204 are suited to the testing substrates 222, 232, the pushing plate 203 is vibrated due to shock from the latch portions 204. Therefore, the semiconductor devices 220, 230 are often displaced which leads to readjustment between the semiconductor devices 220, 230 and the testing substrates 222, 232.